This technology relates to an information processing apparatus, an information processing system, a controlling method for an information processing apparatus and a program, and more particularly to an information processing apparatus, an information processing system, a controlling method for an information processing apparatus and a program wherein a power supply voltage or a frequency is controlled.
In recent years, for a logic circuit for use with a microprocessor or the like, it is often demanded to improve the arithmetic operation process efficiency with respect to power consumption. As a method which improves the arithmetic operation process efficiency by dynamic control without changing the layout of a logic circuit, a method of lowering the power supply voltage while an operating frequency is kept fixed and another method of increasing the frequency while the power supply voltage is kept fixed are available. However, it is known that, when the power supply voltage is lowered or when the frequency is raised, the probability that the logic circuit may malfunction increases.
Errors which make a cause of a malfunction of a logic circuit can be classified into timing violative errors and other errors. A timing violative error is an error caused by displacement of a response timing of the circuit from within an assumed range upon setting.
The errors other than the timing violative errors include an F/F retentive error. The F/F retentive error is an error which occurs because the period for which a flip-flop retains the same value becomes shorter than a value designed therefor.
Since the relationship between the occurrence frequency of such errors and the power supply voltage or frequency varies among various logic circuits, it is difficult to accurately predict a power supply voltage or a frequency across which the error occurrence rate becomes lower than an allowance therefor.
In order to predict a power supply voltage or a frequency across which the occurrence rate of the errors becomes lower than an allowance, it is necessary to investigate the error occurrence rate for each power supply voltage or each frequency on a logic circuit. As a method for detecting an error, a method wherein an EDS (Error Decision Sequentials) and a TRC (Tunable Replica Circuit) are used has been proposed, for example, in James Tschanz et al., “A 45 nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance,” ISSCC 2010. The EDS is a special flip-flop which can detect a timing violative error. The TRC is a circuit wherein inverters are connected such that a delay in a critical path of a logic circuit is imitated so that a data signal delayed by the delay amount is outputted. If a data signal outputted from the TRC is inputted to the EDS and a result of detection of a timing violative error by the EDS is referred to, then presence or absence of occurrence of a timing violative error in the critical path can be predicted.
Further, also a method wherein a TD (Timing-Detector) circuit is used in order to detect an error has been proposed, for example, in David Bull et al., “A Power-Efficient 32b ARM ISA Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation,” ISSCC 2010. The TD circuit detects a rising edge and a falling edge of a data signal to produce a pulse signal and compares production timings of such pulse signals and transition timings of a clock signal with each other to detect an error. A timing violative error in a logic circuit is detected by the TD circuit.
By detecting an error for each of operation conditions in which the power supply voltage or the frequency differs using an EDS and a TRC or a TD circuit, a value of the power supply voltage or the frequency across which the error occurrence frequency becomes lower than an allowance therefor is determined.